A memory controller typically acts as the interface between a memory and one or more data processing components that make use of the memory for storing data. The memory controller therefore is responsible for ensuring proper alignment and interpretation of the various signaling conducted between the memory controller and the memory. However, process, voltage, and temperature (PVT) variations and other factors in the memory system can introduce significant variances in the skew of the signaling throughout the memory system and in the relative signal levels at the input/output (I/O) of the memory controller. As the frequencies increase, this variation becomes more pronounced and makes it more difficult to effectively design an overall memory system. This problem is particularly pronounced in double data rate (DDR) memories due to the use of both the rising edges and falling edges of the reference clock for signaling purposes. Accordingly, a technique for calibrating the memory controller to compensate for the characteristics of the memory system would be advantageous.